==================================================================================== SPC7110F0a Chip information ------------------------------------------------------------- (c) by Kammedo www.yntproject.net, yoninnotranslators@hotmail.com ------------------------------------------------------------- ==================================================================================== This file contains information about the SPC7110F0a chip, which can be found in the following game paks : *Far East Of Eden Zero (FEoEZ) *Super Power League 4 (SPL4) *Momotarou Densetsu Happy (MDH) There are two types of game pak board layouts that use the SPC7110F0a : SHVC-LDH3C-01 FEoEZ game pak board, type 1 SHVC-BDH3B-01 SPL4 and MDH game pak boards, type 2 The difference between the two is represented mainly by the Real Time Clock (RTC) used only in type 1. For the rest, both of them show two separate MASK ROMS (MROM), U1 and U2, U1 containing program data ("8M MROM" on FEoEZ, "P MROM" on the other boards) while U2 contains compressed data ("16/32M MROM" on type 1, "D MROM" on type 2). U2 on type 2 is 40 pins in size, while on type 1 it has 44, which obviously points out at different memory sizes. On both types, The SPC7110F0a uses two (data and address) interfaces, one to the SNES core and one to U2: *the SNES interface has an 8 bit data bus (which is labeled FB1-8 on type 1) and a 24 bit Address bus for both types. *the U2 interface of type 1 uses an 16 (?) bit data bus (SPC Pins 31-34 and 36-39) and a 22 bit Address bus. *the U2 interface of type 2 uses an 16 bit data bus (idem) and a It has both /WR and /RD commands. Actually, no /OE or /CS input has been located. The SPC7110 includes the adress decoding logic for both memory chips and its own. To sustain this theory the facts that U1 /OE (pin 2) is connected to ground, and the /CE (pin 13) come directly from the SPC (pin 47), and the /CE (pin 34) of U2 is connected to ground, while the /OE (pin 36) comes from the pin 48 of the SPC. The addres and data bus of U2 on both board layouts are all directly connected to the SPC7110 only. This makes external addressing impossible; the only way to get to the content of the U2 chip is through the manual decompression mode. (refer to Darkforce's doc, Spc7110r.txt). The U2 on type 1 is 32 Mbit in size. The SPC7110 uses only the lower 8 bits of the U2 on type 1, and D15, but I still can't think about its use. The U2 on type 2 is 32 Mbit in size. Rhe adress lines are shifted by one left (aka SPCA0 on MROMA1) and D15 is used on A0. ================================================================================================================== PINOUTS (based on type 1 Board)! ================================================================================================================== -------------------------------------- Pinout of SPC7110F0a: 80 ...51 81 -------------------- 50 | | | | | | . | | . |* | 31 100-------------------- 1... 30 A) 1-30 This side of the chip interfaces to the Address bus of the SNES and the read/write commands. Pin nr 1 (A8) : SNES-A8 (Conn 9) Pin nr 2 : GND Pin nr 3 (A7) : SNES-A7 (Conn 10) Pin nr 4 (A6) : SNES-A6 (Conn 11) Pin nr 5 (A5) : SNES-A5 (Conn 12) Pin nr 6 (A4) : SNES-A4 (Conn 13) Pin nr 7 (A3) : SNES-A3 (Conn 14) Pin nr 8 (A2) : SNES-A2 (Conn 15) Pin nr 9 (A1) : SNES-A1 (Conn 16) Pin nr 10 (A0) : SNES-A0 (Conn 17) Pin nr 11 : GND Pin nr 12 : Vcc Pin nr 13 (A12) : SNES-A12 (Conn 37) Pin nr 14 (A13) : SNES-A13 (Conn 38) Pin nr 15 (A14) : SNES-A14 (Conn 39) Pin nr 16 (A15) : SNES-A15 (Conn 40) /Type 1, U1_19 Pin nr 17 (A16) : SNES-BA0 (Conn 41) Pin nr 18 (A17) : SNES-BA1 (Conn 42) /Type 1, U1_17 Pin nr 19 (A18) : SNES-BA2 (Conn 43) /Type 1, U1_18 Pin nr 20 (A19) : SNES-BA3 (Conn 44) Pin nr 21 (A20) : SNES-BA4 (Conn 45) Pin nr 22 (A21) : SNES-BA5 (Conn 46) Pin nr 23 (A22) : SNES-BA6 (Conn 47) Pin nr 24 (A23) : SNES-BA7 (Conn 48) Pin nr 25 (/RD) : SNES-/RD (Conn 23) Pin nr 26 (/WR) : SNES-/WR (Conn 54) Pin nr 27 (RESET): SNES-RESET (Conn 26) Pin nr 28 (?1) : Connected through R2 and R3 (serial) and C20 to Connector 1. *So far, on the picture of game pak that can be found on the net, Pin 28 and Pin 29 are connected only by one resistor (R2),and then possibly to Connector 1 (this has to be verified)- Tension Partitioner? Pin nr 29 (?2) : Connected through R3 and C20 to Connector 1 (possible low-pass filter?). Pin nr 30 : GND B) 31-50 This side of the chip interfaces U2 (compressed data ROM) Pin nr 31 : Type 1 U2_D7, Type 2 U2_D7 Pin nr 32 : Type 1 U2_D6, Type 2 U2_D6 Pin nr 33 : Type 1 U2_D5, Type 2 U2_D5 Pin nr 34 : Type 1 U2_D4, Type 2 U2_D4 Pin nr 35 : GND Pin nr 36 : Type 1 U2_D3, Type 2 U2_D3 Pin nr 37 : Type 1 U2_D2, Type 2 U2_D2 Pin nr 38 : Type 1 U2_D1, Type 2 U2_D1 Pin nr 39 : Type 1 U2_D0, Type 2 U2_D0 Pin nr 40 : Vcc Pin nr 41 : GND Pin nr 42 : Type 1 U2_A21 (NC on type 2) Pin nr 43 : Type 1 U2_A20 (NC on type 2) Pin nr 44 : Type 1 U2_A19, Type 2 U2_A20 Pin nr 45 : Type 1 U2_A18, Type 2 U2_A19 Pin nr 46 : GND Pin nr 47 : Type 1 U1_/CE, Type 2 U1_/CE Pin nr 48 : Type 1 U2_/OE, Type 2 U2_/CE Pin nr 49 : Type 1 U2_A17, Type 2 U2_A18 Pin nr 50 : Type 1 U2_A16, Type 2 U2_A17 C) 51-80 This side of the chip interfaces U2 (last Adress data lines and Co.) Pin nr 51 : Vcc Pin nr 52 : GND Pin nr 53 : Type 1 U2_A15, Type 2 U2_A16 Pin nr 54 : Type 1 U2_A14, Type 2 U2_A15 Pin nr 55 : Type 1 U2_A13, Type 2 U2_A14 Pin nr 56 : Type 1 U2_A12, Type 2 U2_A13 Pin nr 57 : Type 1 U2_A11, Type 2 U2_A12 Pin nr 58 : GND Pin nr 59 : Type 1 U2_A10, Type 2 U2_A11 Pin nr 60 : Type 1 U2_A9, Type 2 U2_A10 Pin nr 61 : Type 1 U2_A8, Type 2 U2_A9 Pin nr 62 : Type 1 U2_A7, Type 2 U2_A8 Pin nr 63 : Vcc Pin nr 64 : GND Pin nr 65 : Type 1 U2_A6, Type 2 U2_A7 Pin nr 66 : Type 1 U2_A5, Type 2 U2_A6 Pin nr 67 : Type 1 U2_A4, Type 2 U2_A5 Pin nr 68 : Type 1 U2_A3, Type 2 U2_A4 Pin nr 69 : GND Pin nr 70 : Type 1 U2_A2, Type 2 U2_A3 Pin nr 71 : Type 1 U2_A1, Type 2 U2_A2 Pin nr 72 : Type 1 U2_A0, Type 2 U2_A1 Pin nr 73 : Type 1 U2_D15, Type 2 U2_A0 Pin nr 74 : Vcc Pin nr 75 : GND Pin nr 76 : SRAM 3 (??) Pin nr 77 (RTC_D) : RTC Pin 2 (Data) Pin nr 78 (RTC_CLK): RTC Pin 13 (CLK) Pin nr 79 (/RTC_CE): RTC Pin 12 (/CE) Pin nr 80 : Vcc D)Pin 81-100 This side of the Pin interfaces to the SNES's data bus. Pin nr 81 : Vcc Pin nr 82 : GND Pin nr 83 : GND Pin nr 84 : GND Pin nr 85 : Vcc Pin nr 86 : GND Pin nr 87 (D7): FB8/D7/SRAM10 Pin nr 88 (D6): FB7/D6/SRAM11 Pin nr 89 (D5): FB6/D5/SRAM12 Pin nr 90 (D4): FB5/D4/SRAM13 Pin nr 91 : GND Pin nr 92 (D3): FB4/D3/SRAM14 Pin nr 93 (D2): FB3/D2/SRAM27 Pin nr 94 (D1): FB2/D1/SRAM26 Pin nr 95 (D0): FB1/D0/SRAM25 Pin nr 96 : GND Pin nr 97 : Vcc Pin nr 98 (A11): SNES-A11 (Conn 6) Pin nr 99 (A10): SNES-A10 (Conn 7) Pin nr 100 (A09): SNES-A9 (Conn 8) The following chips can be found on the FEoEZ board (type 1). -------------------------------------- The RTC-4513 chip is mapped as follows. I only include it for completition, you can easily get any Datasheet about it on the net. This chip implements the RTC for the SPC7110F0a. 14.. 8 -------------------- | | |* | -------------------- 1... 7 Note : the "/" in the pin lists is used as a separator. If the signal has a not, there will be two (as "//") Pin 1 : NC Pin 2 : DATA : RTC_S_DATA (SPC Pin 77) Pin 3 : STD.P : NC Pin 4 : NC Pin 5 : NC Pin 6 : Vdd : VCC Pin 7 : NC Pin 8 : NC Pin 9 : GND Pin 10 : NC Pin 11 : NC Pin 12 : CE : RTC_CE (SPC Pin 79) Pin 13 : CLK : RTC_CLOCK (SPC Pin 78) Pin 14 : NC -------------------------------------- The MM1026AF Chip (found on both board layouts)is mapped as follows. I only include it for completition, you can easily get any Datasheet about it on the net. It is used for battery recharging : power source switching for the S-RAM management. Switch to Battery power once the main power turns off. 14.. 8 -------------------- | | |* | -------------------- 1... 7 -------------------------------------- The 8M Mask ROM (U1, SHVC-AZRJ-0 P LH5389N9 9549 D) on type one is mapped as follows : 1... 16 -------------------- | | |* | -------------------- 17... 32 Pin 1 : VCC Pin 2 : /OE Pin 3 : A19 Pin 4 : A14 Pin 5 : A13 Pin 6 :A8 Pin 7 :A9 Pin 8 :A11 Pin 9 :A16 Pin 10 :A10 Pin 11 :/CE Pin 12 :D7 Pin 13 :D6 Pin 14 :D5 Pin 15 :D4 Pin 16 :D3 Pin 17 :A17 Pin 18 :A18 Pin 19 :A15 Pin 20 :A12 Pin 21 :A7 Pin 22 :A6 Pin 23 :A5 Pin 24 :A4 Pin 25 :A3 Pin 26 :A2 Pin 27 :A1 Pin 28 :A0 Pin 29 :D0 Pin 30 :D1 Pin 31 :D2 Pin 32 :GND -------------------------------------- The 16/32M Mask ROM (U2, SHVC-AZRJ-0 D LH535KN2 9550 E) on type 1 is mapped as follows : 1... 22 -------------------- | | |* | -------------------- 23... 44 Pin 1 : A20 Pin 2 : A19 Pin 3 : A08 Pin 4 : A09 Pin 5 : A10 Pin 6 : A11 Pin 7 : A12 Pin 8 : A13 Pin 9 : A14 Pin 10 : A15 Pin 11 : A16 Pin 12 : +5V Pin 13 : GND Pin 14 : D15 Pin 15 : D7 Pin 16 : D14 Pin 17 : D6 Pin 18 : D13 Pin 19 : D5 Pin 20 : D12 Pin 21 : D4 Pin 22 : VCC Pin 23 : A21 Pin 24 : A18 Pin 25 : A17 Pin 26 : A7 Pin 27 : A6 Pin 28 : A5 Pin 29 : A4 Pin 30 : A3 Pin 31 : A2 Pin 32 : A1 Pin 33 : A0 Pin 34 : /CE Pin 35 : GND Pin 36 : /OE Pin 37 : D0 Pin 38 : D8 Pin 39 : D1 Pin 40 : D9 Pin 41 : D2 Pin 42 : D10 Pin 43 : D3 Pin 44 : D11 1... 20 -------------------- | | |* | -------------------- 21... 40 -------------------------------------- The D and P MROM chips on type 2 have the following layout : Pin 1: Vcc Pin 2: Vcc Pin 3: Vcc Pin 4: A22 Pin 5: Vcc Pin 6: /OE Pin 7: A19 Pin 8: A14 Pin 9: A13 Pin 10: A8 Pin 11: A9 Pin 12: A11 Pin 13: A16 Pin 14: A10 Pin 15: /CE Pin 16: D7 Pin 17: D6 Pin 18: D5 Pin 19: D4 Pin 20: D3 Pin 21: GND Pin 22: GND Pin 23: A20 Pin 24: A21 Pin 25: A17 Pin 26: A18 Pin 27: A15 Pin 28: A12 Pin 29: A7 Pin 30: A6 Pin 31: A5 Pin 32: A4 Pin 33: A3 Pin 34: A2 Pin 35: A1 Pin 36: A0 Pin 37: D0 Pin 38: D1 Pin 39: D2 Pin 40: GND -------------------------------------- The 64K SRAM Chip (HY6264A LLJ-10) is mapped as follows: SRAM (8KB) 6264 Pinout: __ __ +5V |01\/28| +5V A12 |02 27| :WE A7 |03 26| RESET A6 |04 25| A8 A5 |05 24| A9 A4 |06 23| A11 A3 |07 22| :OE A2 |08 21| A10 A1 |09 20| :CE A0 |10 19| D7 D0 |11 18| D6 D1 |12 17| D5 D2 |13 16| D4 GND |14 15| D3 ------ pin :CE connected to Address Decoder pin :OE connected to :CE in ROM pin :WE connected to SNES pin #54 pin #26 connected to SNES pin #26 (RESET) and MAD-1 pin #09 ================================================================================================================== Memory Mapper $3F (courtesy of Charles MacDonald, cgfm2.emuviews.com) ================================================================================================================== Banks 00-1F : SRAM @ 6000-7FFF, U1 ROM @ 8000-FFFF (1MB) 20-3F : SRAM @ 6000-7FFF, U2 ROM @ 8000-FFFF (banked?) 40-4F : Unused (reads return last value on data bus; e.g. bank address) 50 : 64K SPC7110 internal RAM 51-57 : Unused (as above) 58 : SPC7110 data port 59-7D : Unused (as above) 80-9F : 8K SRAM @ 6000-7FFF, U1 ROM @ 8000-FFFF (1MB) A0-BF : 8K SRAM @ 6000-7FFF, U2 ROM @ 8000-FFFF (banked?) C0-CF : U1 ROM (1MB) D0-DF : U2 ROM (banked) E0-EF : U2 ROM (banked) F0-FF : U2 ROM (banked) ================================================================================================================== SELF CHECK INFORMATION ================================================================================================================== *The text of the test screens is located at ROM location $CFF022. There is no table. This bitch is coded in a (to me at least) orginal fashion. The routine that loads the byte sequence starts at $CFE358. *At $CFF150 the ROM presents the test values used for testing the SRAM (in the format SRAM_OFFSET/VALUE, 2 bytes each). The SPC Check presents two modes - MODE 1 and MODE 2. MODE 1 ---------------------- MODE 1 is accessed by pressing the A button at the first boot up. By activating the SRAM (#$80 to $4830)the SNES compares the last 16 bytes of it with the text located at ROM addr. $C02F25 (SNES addr format) - the infamous "SPC7110 CHECK OK". If more than 3 bytes are not matching,it starts the self tests. REG INIT Firstly it checks the SPC's registers via a simple read/compare action. The registers to test are defined in a table located at $CFF1B9 (Snes addr. format). The compared values are stored at offset $CFF211 (1 Byte, 4 values). Specifically, those values are used to check the SPC ROM Bank mapping regs ($4831-33) & SRAM ($4830). Apparently, on boot the SRAM should result not active ($4830=$00), and the three mappings #$00, #$01, #$02 (from A to C the same order). S-RAM DATA BUS The SRAM is initialized one byte at a time to $FF (via the $00:6000 bus). The tests firstly check the first 8 bytes of the DROM (sequence :0102040810204080) and then the 8 last ones (sequence :FEFDFBF7EFDFBF7F, which is the first sequence ex-ored). MODE 2 ---------------------- MODE 2 is accessed by pressing the B button at the first boot up, or at the second if test in MODE 1 has been succesfully performed. It checks for a SRAM and RTC backup. The following is checked: *TODO' *Does it skip the tests if a joy pad key is pressed? ========================================================================================== CREDITS *First Credit goes to Darkforce, mentor of DeJap, great ASM & ROM Hacker. He dumped the whole Graphics packs, with the great help of The Dumper - if it wasnt for those two you still would not be playing FEoEZ & Co! *The pinouts of the 16/32M and 8M ROM, type two MROMS's as well as the SRAM pinouts can be found here : http://nintendoallstars.w.interia.pl/romlab/sneslab.htm - siudym@pf.pl ==========================================================================================